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Altera_Forum
Honored Contributor
Honored Contributorinfer true dual port asynchronous ram
hallo everyone, i need a true dual port asynchronous ram for my selfmade soft-core project. to be hardware independent i try to infer the ram-block from vhdl-code. this is my code: ...
Altera_ForumHonored Contributor
Honored Contributorthanks for your fast answer.
the quartus megafunctions supports asynchronous dual port ram. and the synthesis seems to be correct (although i have not tested it on my cyclone II board), so i thought that should be possible in vhdl too.
