Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

infer true dual port asynchronous ram

hallo everyone, i need a true dual port asynchronous ram for my selfmade soft-core project. to be hardware independent i try to infer the ram-block from vhdl-code. this is my code: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

thanks for your fast answer.

the quartus megafunctions supports asynchronous dual port ram. and the synthesis seems to be correct (although i have not tested it on my cyclone II board), so i thought that should be possible in vhdl too.