infer true dual port asynchronous ram

I seem to recall a discussion on comp.lang.VHDL a while ago about this very issue.

IIRC, the conclusion was that Xilinx devices changed read-during-write behaviour when you swapped RAM between a signal and a shared variable. For Altera, when it did compile (I cant remember whether reset and enable inputs were included) there was no difference between the shared variable and signal versions. This meant that to modify the behaviour you had to use the altsyncram megafunction.

I think I found the discussion:

http://groups.google.com/group/comp.lang.vhdl/browse_frm/thread/b4b6147c98e6af5a/81d7b4efdc6ce246?lnk=gst&q=dual+port+ram#81d7b4efdc6ce246