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Altera_Forum
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15 years ago

infer true dual port asynchronous ram

hallo everyone, i need a true dual port asynchronous ram for my selfmade soft-core project. to be hardware independent i try to infer the ram-block from vhdl-code. this is my code: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You should consider the hardware differences to understand the different behaviour.

Xilinx actually has asynchronous (unregistered) RAM with all FPGA series as far as I'm aware of, Altera hasn't. Furthermore, inference of asynchronous RAM seems not to work even with those Altera Stratix devices, that have the option in hardware.

You can review the Quartus VHDL templates to see which RAM constructs are supported for inference.