infer true dual port asynchronous ram

ok...its not the best way...but now i am using the megafunctions in my vhdl description.

but at synthesis appeared an other problem.

configuration of my altsyncram:

- two read/write ports (true dual-port mode)

- 256 words (word = 16 bits) -> 256x16

- dual clock: use seperate clocks for A and B ports

- create one clock enable signal for each clock signal

so the total used memory bits should be 256*16 = 4096 bits

but the synthesis uses 8192 bits (2 M4Ks).

is this the correct behaviour? i have not find any application note to this topic.

i am using a cyclone II device

edit:

i have tested the megafunction with Input/Output and Single Clock mode. in both cases the synthesis uses 1 M4K cell.