How to simulate the FPGA neural network in Altera

If u are creating a new project,i believe that u already has at least a device family installed in the Quartus because u'll need to choose from the listed part numbers for the design u are creating for.

And make sure u open a project NOT a file in the Quartus for u to able to compile the project design.

Yes I create project not file. But Create not Open.

http://postimg.org/image/m3qrcpqlj/ -- here is the logic circuit that I need to implement. At least in Micro-cap and simulink it should be done without the iterations and Neural Networks. So Could it be donhe in Altera on Verilog. What is the main difficlulties. S --comparator, there is also inverted integartor on time, that multiplies on coeficient alpha(about 1000)--so I do think it could be easier to do in Verilog then Micro-cap for example as there is no libraries for multiplier, even adder, substractor. The only difficult line is integartor..What would you suggested? Sn+2=x-A; Sn+1=x; depending on the K-Sum of Step functions An-X (intial x should be 0--but it is the main bottleneck as x begin rise on some expotential rule). And I am not aware of the fucntion of analog integrator --al other components should be analog, as the source signals should be constant.

for Example could I simply use code line "An-Amin+x" in verilog for this adder, and integrator *(-Alpha) for the node around the integartor. The fucntion of integartor is dx=x or x-A; so I do understand that x^2/2=x or x-A; or I am not correct as it is integrating for the time, but internal integral seems to be taking into account as far as I remember since mathematics. Or what such (x)=x should mean? if (x) is the derivative?

if i were to make a neural network fpga project I would do the following:

I do not know simulink a lot. So I will try to implement it in microcar with the macros of integrator, comparator, adder and so on. But the main issue - shout it be implemented in one cycle or it is needed several iterations. Is it possible to simulate neural network in simulink with the several iterations? As well in altera. As I have just the logic circuit and I need to find the level of shift x that would minimize the function E.

So what is difference between labview fpga and altera fpga. As I have two task but do not know difference?

Labview FPGA uses National Instruments (NI) tools and Xilinx FPGAs such as Spartan, Virtex, etc. I've never used Xilinx fpgas before, but I have used Labview as a stand alone solution. Labview is similar to Matlab/ simulink. My guess is that Xilinx provides a tool that can convert Labview designs into synthesizable HDL for their FPGAs. Similarly, Altera provides DSP Builder Blockset that can convert Simulink designs into HDL.

Thank you for the last cues. But I would also like how to convert labview design to hdl by xilink tools. Can I simply convert by some button or function. Or I should rewrite the whole structure of labview diagrams? And about simulink convertion. Can I convert it also directly. Or I should substitute every block of simulink to dsp blockset? Should I use simulink blocks or matlab code to make file for conversion. As my teacher said that circuit is implemented in simulink code but how? It is easy on his mind.