How to simulate the FPGA neural network in Altera

It is about 3 month since the last post -- but I wanted to have real understanding of this whole subject, so next set of questions. So about z-transform -- the resource is not very easygoing. What about testbench -- as it is for simulation and since I have no device -- I understand that I need to have all code for the testbench -- e.g. for the simulation? Or testbench is just a part of code and all other could be got from conversion from Simulink for example? And why testbenchis more or just for VHDL not Verilog? Next question -- I have read that in logical devices the signals could not be permanent so I understand that the RESET is for support of its constantness and clock is some signall that stimulate change in other signalls -- so what is differense between clock signal and other in and out signals as the difference even in description in schematics (arrows and circles). And the one more question -- what book or tutorial I can grasp the computer and schematic basis for vhdl and verilog as I am not from english-speaking and western european counry