How to simulate the FPGA neural network in Altera

But it is example on VHDL. It would be better to write in Verilog.

From another hand -- I was found a lot of files about Verilog testbench -- but it is not so easy to undestand despite I was theoretically

accustomized in Verilog.

And I do not understand why when i converted my simulink design (despite not converting in fixed point) I have got abou 6-8 thousands lines of verilog code?

And if it is so simple, despite you have written otherwise above, what is rule to apply this testbench -- why clock should be apply here -- to what component of circuit it should apply--should it be once-- then what is the role of reset--shoud it apply for every "clock" when one of two different of wires go inside integrator (with minus or plus values; 0 value is final third condition when system is optimized) -- I am not very awares of these features of digital circuits.

And if I pass for input such values 2,5, 7, 11, 14..what types of input I should use. Shoudl it be 4-bit as 14 is 1110, then I multilpy for 20 --should I use n-bit for 280. And of kind of output I should use --just the 1 as winner and 0 for other types?