How to simulate the FPGA neural network in Altera

Everything you asked has been answered in this thread, but I'll explain again:

1) Modelsim does not allow mixing of languages (on a free license), therefore since the DSP code is in VHDL, the testbench also has to be in VHDL.

2) Your conversion may be different because you were using HDL coder, while I used Altera's DSP builder. The code i got is about 1.3k lines.

3) in the testbench you set up your clock, resets and inputs: the clock I used was 500kHz. The reset is used to initialize values in synchronous processes. Since the DSP builder code is set for an active high reset, you must keep the reset high for at least 1 clock cycle, and then bring it low. The other inputs include valid, channel, and the 6 data inputs. The Valid signal is high (1) every 5 clock cycles in my design. This allows for the integrator loop to process before new data comes in. The channel input is always 0, we have 6 simultaneous inputs, no data is being multiplexed. The 6 inputs are your data.

The VHDL code I provided includes the whole NN. All you need to do in connect the inputs, the clock (only 1 clock is used), and the reset and then look at the outputs.

4) My circuit is a 1 winner takes all - therefore only one of the outputs will be > 0. The inputs are set to 12 bit values. Therefore 14 is "000000001110". If you use 4 bit values, you can only input values <16. Using 12 bit you can use values <2^12