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Honored Contributor
Honored ContributorHow to simulate the FPGA neural network in Altera
I want to simulate the some kind of schematics that work by principle of neural networks. I have Altera Quadrus 11. But when trying create some verilog or vhdl code I see that compilation and simul...
Altera_ForumHonored Contributor
Honored ContributorOh, I understand the wave charts can just produce the signal of level of 1 or 0 so here is no nesessity to use comparator to transform the n>0 to 1 and m<=0 to 0. But is it impossible to show the decerasing for example the initial signal from 7 to 2 with almost linear decrease and then with horizonal line of final level?
Then could you explain what is the role of clock, reset? What is difference? What influence one and what the other. Which influence the integrator discrete addings (how find the integrator code in HDL generator), and what RESET reset?
