Forum Discussion
Altera_Forum
Honored Contributor
10 years agoThe VHDL testbench is very simple to write. It's 1 file and few lines of code. Here is a guide: http://vhdlguru.blogspot.com/2010/03/how-to-write-testbench.html
The WTA net is the same algorithm as in the simulink files set for 1 winner and 6 inputs. The VHDL code was generated using DSP builder. If you have Quartus, then you also have Altera's version of ModelSim. You just need to start a project in model sim and drop in the VHDL files and your testbench. Make sure your libraries are properly set up. I can't help you with Xilinx b/c I don't use Xilinx. This code probably won't run in with Xilinx tools b/c it is generated based on Altera's libraries.