Honored Contributor
Honored ContributorA simulation is used to simulate "the outside world" so this couldbe switches that the user presses r signals coming from other chips. It can also be used to check the output values of your design. I think Simulink can provide a framework for the testbench, but I am not sure about that.
A reset is used to force the device into a known state, this usualy means clearing the data. The clock is used to limit the changes in data values. If you use memory this memory will require the data to be stable for a set period. By only allowing datachanges on a clock edge the data will become stable afte a while. If your design is correctly done this means all the manipulations are done before the next triggering edge. Why does the data need to be stable? Lets say a 1 is represented by 5 Volts ans a 0 by 0Vm(I don't think these are the values used in an FPGA). If you change from one to the other this takes time (slew rate). So what value should be assigned to a 2.5 volt signal? In practice ranges are defined so a 1 is everything between 5 and 3 volt and a 0 is assigned to everything between 2 and 0. But you will always have that small undefined gap. A clock is used to prevent the value from bei g mid-transition when read by a memory element. As for information on VHDL or Verilog, search the forum for books. There are enouh threads that provide infor ation on good ones. One of them: http://www.alteraforum.com/forum/showthread.php?t=41998&highlight=books+vhdl i don't know any good books in a language other than english. (http://www.alteraforum.com/forum/showthread.php?t=41998&highlight=books+vhdl)
