How to simulate the FPGA neural network in Altera

Yes you can see the decreasing signal in the wave chart by changing the "Format" from "Literal" to "Analog". It will display a plot instead of showing actual values.

Clock is the system clock of the design. In FPGA designs everything is synchronized to the rising edge of a clock. In this case the system clock is 50kHz (20000 ns period). Then there is the "Valid" signal. This states when new data is coming in. In this design it is set to 10kHz. So every 5 clock cycles, the design logs new incoming data. This is done so that internal portions of the design (like the integrator) can complete their arithmetic loops before new data comes in. The "Reset" signal is used just initially to set everything to 0, otherwise some outputs (like multiplier outputs) can initialize with unknowns ("X") and propagate Xs through the design.

If you open up the zip file, it includes the simulink file using DSP blockset. You will see that the integrator is described using discrete blocks: a delay (z^-5), adder, multiplier, because a discrete integrator is of the form: Y(z) = T*X(z) + z^-1 * Y(z)

(I use z^-5 because sample delays refer to system clock - 50kHz - while my data rate is 10 kHz. The integrator delay in the equation above is referenced to the data delay).