How to set multicycle for this design?

sorry, should "start" instead of "end".

set_multicycle_path -from reg1 -to reg2 -start -setup 4

set_multicycle_path -from reg1 -to reg2 -start -hold 3

A setup multi-cycle exception of N means that the path always has, at least, N cycles to propagate the signal.

So, you need to figure out how many cycles each path has, in the worse case scenario.

If all you have are the enables then

- reg1 to reg2 should not have a multi-cycle exception, since reg1's output may change just 1 clock before reg2 captures.

- reg2 to reg3 should have a multi-cycle exception of 4 (3 for hold), because you're guaranteeing that reg2's output changes 4 cycles before reg3 captures, every time.

- reg3 to reg4 again should have a multi-cycle exception of 4 (3 for hold) because, again, reg3's output may change only 4 cycles before.

The -start and -end options don't have effect, since the start and end are in the same clock.

Hei, I have a further question here:

If reg2 is enabled when clock_enable_counter=0, while reg3 is enabled when clock_enable_counter=3, this means reg2 is 3 clock cycles earlier than reg3, what correct multicycles should be set now? I'm thinking setup 7, hold 3, is it correct? Could anybody tell me? Any help is appreciated!!!

It's setup 3, because the path has 3 cycles to work with.

Hold is 2. In this application, the hold multiplier is always N-1.

rbugalho, thanks very much for the nice answer.

But I do not understand why setup 3, hold 2.

In my design,

I simply my code in the attachement, I'm wondering how should I set multicycle to reg2 to reg3, because different bit of reg2 is enabled by different clock_enable_counter.

Should I set constraint like this?

from ret2[0] to reg3[0], setup is 3, hold is 2, then

from ret2[1] to reg3[1], setup is2, hold is 1,

from ret2[2] to reg3[2], setup is 1, hold is 0, as default.

from ret2[3] to reg3[3], setup is 4, hold is 3

or I should set

from ret2[0] to reg3[0], setup is 7, hold is 6, then

from ret2[1] to reg3[1], setup is 6, hold is 5,

from ret2[2] to reg3[2], setup is 5, hold is 4

from ret2[3] to reg3[3], setup is 4, hold is 3

Which one is correct?

Also from reg3 to reg4, and reg4 to reg5, can I set multicycle for those path, reg4and reg5 are clocked by 100MHz, but the original data (from reg3) would change every 4 clock cycles, perhaps it is possible to set multicycle to these paths?

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity rx_tapering_core is

port (

clk_4x : in std_logic; --(100MHz)

reset : in std_logic;

clock_enable_counter : in unsigned(1 downto 0);--(downscale data rate to 25MHz)

clock_downsampler_en_counter : in unsigned(1 downto 0);--(downscale data rate to 6.25MHz)

data_in : in std_logic_vector(3 downto 0);

);

end entity rx_tapering_core;

architecture rtl of rx_tapering_core is

signal reg1 : std_logic(3 downto 0);

signal reg2 : std_logic(3 downto 0);

signal reg3 : std_logic(3 downto 0);

signal reg4 : std_logic(3 downto 0);

signal reg5 : std_logic(3 downto 0);

signal reg6 : std_logic(3 downto 0);

begin

p_rx_tapering : process (clk_4x, reset)

variable mult_res : signed(20 downto 0);

begin

if (reset = '1') then

reg1 <= (others=>'0');

reg2 <= (others=>'0');

reg3 <= (others=>'0');

reg4 <= (others=>'0');

reg5 <= (others=>'0');

reg6 <= (others=>'0');

elsif rising_edge (clk_4x) then

reg1 <= data_in;

case clock_enable_counter is

when "00" =>

reg2(0) <= reg1(0);

when "01" =>

reg2(1) <= reg1(1);

when "10" =>

reg2(2) <= reg1(2);

when others =>

reg2(3) <= reg1(3);

end case;

--Multiplexer that provides 8 channels as input to multipliers

case clock_enable_counter is

when "00" =>

data_mux_out <= data_in_d1(95 downto 0);

when "01" =>

data_mux_out <= data_in_d1(191 downto 96);

when "10" =>

data_mux_out <= data_in_d1(287 downto 192);

when others =>

data_mux_out <= data_in_d1(383 downto 288);

end case;

if clock_enable_counter = 3 then

reg3 <= reg2;

end if;

reg4 <= reg3;

reg5 <= reg4;

if (clock_enable_counter = 3 and clock_downsampler_en_counter = 0) then

reg6 <= reg5;

end if;

end if;

end process p_rx_tapering;

end architecture rtl;

Sorry, the following code should be removed,

in --Multiplexer that provides 8 channels as input to multipliers

case clock_enable_counter is

when "00" =>

data_mux_out <= data_in_d1(95 downto 0);

when "01" =>

data_mux_out <= data_in_d1(191 downto 96);

when "10" =>

data_mux_out <= data_in_d1(287 downto 192);

when others =>

data_mux_out <= data_in_d1(383 downto 288);

You need to figure out, from your design, what's the worse case minimum number of cycles you have from registerA launching data and registerB capturing data.

Look at your logic, look at your waveforms.

And that will be your setup multiplier factor N.

From your earlier description, if regA launches 3 cycles earlier than regB captures, then N is 3.

I have no idea how you got from understanding that you have 3 cycles to thinking about a multicycle exception of 7.

The hold multiplier needs to be set to N-1.

This document will explain it better than I ever will: http://www.scribd.com/doc/14475172/multi-cycle-paths

Since you have different bits with different enables, then you need to use separate multicycle exceptions for each bit.

Hi rbugalho,

Thanks very much for the reply. I simulated the waveform, I found I was wrong.

I think it should be the first case, from reg2[0] to reg3[0], setup is 3, hold is 2, then

from ret2[1] to reg3[1], setup is2, hold is 1,

from ret2[2] to reg3[2], setup is 1, hold is 0, as default.

from ret2[3] to reg3[3], setup is 4, hold is 3

I understand why from ret2[3] to reg3[3], setup is 4, hold is 3.

But from reg2[0] to reg3[0], I know setup is 3, but I do not know why hold is 2, because in this case, reg3 is enabled every 4 clock cycles, so if the previous latch clock is should be one clock cycle before the current launch clock. So I'm thinking the hold should be also 3. Perhaps I'm wrong, but I do not know.

Perhaps the hold check should always be 0?

The hold multiplier has to do with the semantics of the set_multicycle_path command.

It's a bit confusing and one could argue that Synopsis (who originally created the SDC command set) could have done it differently, but it is what it is.

If you take a look at the document I linked, figure 0-2, you see what happens when you specify a setup multiplier of 5 and and leave the hold multiplier at 0 (default): the hold check is still moved, to the previous edge to the setup check.

What this means is that, in order to meet hold requirements in Figure 0-2, the actual delay must be >= 4 clocks. And <= 5 clocks to meet the setup requirements, of course.

When dealing with clock enabled and such, you have no need for such a huge delay.

So, we need to set a hold multiplier of 5-1 to move the hold check back (Figure 0-3).

This means that the delay must be >= 0 to meet hold requirements, and <= 5 to meet setup requirements. Which is what we want.

That's why it's always N-1.