How to set multicycle for this design?

You need to figure out, from your design, what's the worse case minimum number of cycles you have from registerA launching data and registerB capturing data.

Look at your logic, look at your waveforms.

And that will be your setup multiplier factor N.

From your earlier description, if regA launches 3 cycles earlier than regB captures, then N is 3.

I have no idea how you got from understanding that you have 3 cycles to thinking about a multicycle exception of 7.

The hold multiplier needs to be set to N-1.

This document will explain it better than I ever will: http://www.scribd.com/doc/14475172/multi-cycle-paths

Since you have different bits with different enables, then you need to use separate multicycle exceptions for each bit.