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Honored Contributor
Honored ContributorHow to set multicycle for this design?
In my design, all clocks are clka (100 MHz), but clock enables are used to make registers change at 25 MHz or 6.25 MHz. The signal path is reg1(clka,100MHz)->reg2(enable to 25 MHz, clocked by cl...
Altera_ForumHonored Contributor
Honored ContributorHi rbugalho,
Thanks very much for the reply. I simulated the waveform, I found I was wrong. I think it should be the first case, from reg2[0] to reg3[0], setup is 3, hold is 2, then from ret2[1] to reg3[1], setup is2, hold is 1, from ret2[2] to reg3[2], setup is 1, hold is 0, as default. from ret2[3] to reg3[3], setup is 4, hold is 3 I understand why from ret2[3] to reg3[3], setup is 4, hold is 3. But from reg2[0] to reg3[0], I know setup is 3, but I do not know why hold is 2, because in this case, reg3 is enabled every 4 clock cycles, so if the previous latch clock is should be one clock cycle before the current launch clock. So I'm thinking the hold should be also 3. Perhaps I'm wrong, but I do not know. Perhaps the hold check should always be 0?
