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Honored Contributor
Honored ContributorHow to set multicycle for this design?
In my design, all clocks are clka (100 MHz), but clock enables are used to make registers change at 25 MHz or 6.25 MHz. The signal path is reg1(clka,100MHz)->reg2(enable to 25 MHz, clocked by cl...
Altera_ForumHonored Contributor
Honored ContributorThe hold multiplier has to do with the semantics of the set_multicycle_path command.
It's a bit confusing and one could argue that Synopsis (who originally created the SDC command set) could have done it differently, but it is what it is. If you take a look at the document I linked, figure 0-2, you see what happens when you specify a setup multiplier of 5 and and leave the hold multiplier at 0 (default): the hold check is still moved, to the previous edge to the setup check. What this means is that, in order to meet hold requirements in Figure 0-2, the actual delay must be >= 4 clocks. And <= 5 clocks to meet the setup requirements, of course. When dealing with clock enabled and such, you have no need for such a huge delay. So, we need to set a hold multiplier of 5-1 to move the hold check back (Figure 0-3). This means that the delay must be >= 0 to meet hold requirements, and <= 5 to meet setup requirements. Which is what we want. That's why it's always N-1.
