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Honored Contributor
Honored ContributorHow to set multicycle for this design?
In my design, all clocks are clka (100 MHz), but clock enables are used to make registers change at 25 MHz or 6.25 MHz. The signal path is reg1(clka,100MHz)->reg2(enable to 25 MHz, clocked by cl...
Altera_ForumHonored Contributor
Honored ContributorHei, I have a further question here:
If reg2 is enabled when clock_enable_counter=0, while reg3 is enabled when clock_enable_counter=3, this means reg2 is 3 clock cycles earlier than reg3, what correct multicycles should be set now? I'm thinking setup 7, hold 3, is it correct? Could anybody tell me? Any help is appreciated!!!
