How to set multicycle for this design?

rbugalho, thanks very much for the nice answer.

But I do not understand why setup 3, hold 2.

In my design,

I simply my code in the attachement, I'm wondering how should I set multicycle to reg2 to reg3, because different bit of reg2 is enabled by different clock_enable_counter.

Should I set constraint like this?

from ret2[0] to reg3[0], setup is 3, hold is 2, then

from ret2[1] to reg3[1], setup is2, hold is 1,

from ret2[2] to reg3[2], setup is 1, hold is 0, as default.

from ret2[3] to reg3[3], setup is 4, hold is 3

or I should set

from ret2[0] to reg3[0], setup is 7, hold is 6, then

from ret2[1] to reg3[1], setup is 6, hold is 5,

from ret2[2] to reg3[2], setup is 5, hold is 4

from ret2[3] to reg3[3], setup is 4, hold is 3

Which one is correct?

Also from reg3 to reg4, and reg4 to reg5, can I set multicycle for those path, reg4and reg5 are clocked by 100MHz, but the original data (from reg3) would change every 4 clock cycles, perhaps it is possible to set multicycle to these paths?

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity rx_tapering_core is

port (

clk_4x : in std_logic; --(100MHz)

reset : in std_logic;

clock_enable_counter : in unsigned(1 downto 0);--(downscale data rate to 25MHz)

clock_downsampler_en_counter : in unsigned(1 downto 0);--(downscale data rate to 6.25MHz)

data_in : in std_logic_vector(3 downto 0);

);

end entity rx_tapering_core;

architecture rtl of rx_tapering_core is

signal reg1 : std_logic(3 downto 0);

signal reg2 : std_logic(3 downto 0);

signal reg3 : std_logic(3 downto 0);

signal reg4 : std_logic(3 downto 0);

signal reg5 : std_logic(3 downto 0);

signal reg6 : std_logic(3 downto 0);

begin

p_rx_tapering : process (clk_4x, reset)

variable mult_res : signed(20 downto 0);

begin

if (reset = '1') then

reg1 <= (others=>'0');

reg2 <= (others=>'0');

reg3 <= (others=>'0');

reg4 <= (others=>'0');

reg5 <= (others=>'0');

reg6 <= (others=>'0');

elsif rising_edge (clk_4x) then

reg1 <= data_in;

case clock_enable_counter is

when "00" =>

reg2(0) <= reg1(0);

when "01" =>

reg2(1) <= reg1(1);

when "10" =>

reg2(2) <= reg1(2);

when others =>

reg2(3) <= reg1(3);

end case;

--Multiplexer that provides 8 channels as input to multipliers

case clock_enable_counter is

when "00" =>

data_mux_out <= data_in_d1(95 downto 0);

when "01" =>

data_mux_out <= data_in_d1(191 downto 96);

when "10" =>

data_mux_out <= data_in_d1(287 downto 192);

when others =>

data_mux_out <= data_in_d1(383 downto 288);

end case;

if clock_enable_counter = 3 then

reg3 <= reg2;

end if;

reg4 <= reg3;

reg5 <= reg4;

if (clock_enable_counter = 3 and clock_downsampler_en_counter = 0) then

reg6 <= reg5;

end if;

end if;

end process p_rx_tapering;

end architecture rtl;