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Honored Contributor
Honored ContributorHow to set multicycle for this design?
In my design, all clocks are clka (100 MHz), but clock enables are used to make registers change at 25 MHz or 6.25 MHz. The signal path is reg1(clka,100MHz)->reg2(enable to 25 MHz, clocked by cl...
Altera_ForumHonored Contributor
Honored ContributorA setup multi-cycle exception of N means that the path always has, at least, N cycles to propagate the signal.
So, you need to figure out how many cycles each path has, in the worse case scenario. If all you have are the enables then - reg1 to reg2 should not have a multi-cycle exception, since reg1's output may change just 1 clock before reg2 captures. - reg2 to reg3 should have a multi-cycle exception of 4 (3 for hold), because you're guaranteeing that reg2's output changes 4 cycles before reg3 captures, every time. - reg3 to reg4 again should have a multi-cycle exception of 4 (3 for hold) because, again, reg3's output may change only 4 cycles before. The -start and -end options don't have effect, since the start and end are in the same clock.
