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Altera_Forum's avatar
Altera_Forum
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13 years ago

How to set multicycle for this design?

In my design, all clocks are clka (100 MHz), but clock enables are used to make registers change at 25 MHz or 6.25 MHz. The signal path is reg1(clka,100MHz)->reg2(enable to 25 MHz, clocked by cl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Sorry, the following code should be removed,

in --Multiplexer that provides 8 channels as input to multipliers

case clock_enable_counter is

when "00" =>

data_mux_out <= data_in_d1(95 downto 0);

when "01" =>

data_mux_out <= data_in_d1(191 downto 96);

when "10" =>

data_mux_out <= data_in_d1(287 downto 192);

when others =>

data_mux_out <= data_in_d1(383 downto 288);