How to set clock controller in BTS (board_test_system) for 32G (NRZ) MXP BTS example

Dear support:

Please help me clarify this issue.

Thanks.

Regards,

Ming

Hi,

First of all, you have to change the IP configuration of F-tile DPHY and the system PLL IPs in the design. Usually the complete Quartus project is for the example .sof files is provided in the 'examples' folder.

If you have already done those changes in your custom design then the sequence would be:

1) Understand the refclk pin used for the driving the channels from the Schematics. I believe these are F-tile FHT channel XCVR pins.

2) Trace the refclk pin to its source. It must be connected to one of the OUT pins of the clock source. Example: Si5394 (U118) OUT0.

3) Click on the "Clock" button under Utilities box on the BTS home page.

4) Locate the source IC (Si5394) from the multiple tabs: 4.3. Control On-Board Clock through Clock Controller GUI

5) Change to the required frequency for 32G configured in the F-tile system PLL IP.

6) Make sure that the input data rate at the XCVR pin is as per the configuration in the F-tile DPHY IP.

Hope this helps.

Regards

Hi Ash_R:

Thanks for your support, it has been helpful.

We are unable to change the frequency to 32G configured in the F-tile using clock utilities.

as the system is rejecting our updated values.

Please refer the attached file.

I have a few questions as follows.

The default clock setting, it can run at 25.78118G Hz.

What reference clock values would allow the SerDes run at 32GHz?

Could you provide any refer documents for different data rate applications ?

Are there any constrains or limitations on setting the clock values?

Thanks again for your assistance.

Regards,

Ming

Hi Ash_R:

I provide more information as follows

1. The current BTS (board test system) has been configured as MXPM_FGT x4

(25.78118Gbps) , and the loopback function works well.

2. if we change the clock rate using the clock controller (ex. OUT2

156.25MHz-->148.5MHz (or 184.32MHz) ), the system hangs.

How to change the clock for MXPM_FGT x4 32Gbps ?

Thanks.

Regards,

Ming

Hi,

The provided .sof file might have been generated only to support that data rate.

To achieve the data rate of 32Gbps, you will be required to change the F-tile DPHY and system PLL IP settings accordingly.

The related Quartus project can be found in following directory of the installer package:

<installation_package>\examples\bts_xcvr_nrz\MXPM\bts_xcvr_mxpm_nrz_224.zip\bts_xcvr_mxpm_nrz_224

Refer to 3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP and 4. Implementing the F-Tile Reference and System PLL Clocks Intel®...

Regards,

Ashlesha

Hi,

For the version that you are referring to, please find the Quartus design in following path:

<installation_package>\examples\bts_xcvr\bts_xcvr_nrz\bts_xcvr_mxpm_25.78125gbps_nrz.zip\

Regards

Hi,

As I mentioned in one of my previous comment that the design for MXPM should be modified by the user as per the data rate required.

We do not have a direct example for 32Gbps, but as per the datasheet the device does support it.

Please refer to the F-tile User Guide: 1. F-Tile Overview

Regards

As the recommendations has been provided, I am setting the case to closure. However, it will still be open for the community members to comment on.

Regards