How to set clock controller in BTS (board_test_system) for 32G (NRZ) MXP BTS example

Hi,

First of all, you have to change the IP configuration of F-tile DPHY and the system PLL IPs in the design. Usually the complete Quartus project is for the example .sof files is provided in the 'examples' folder.

If you have already done those changes in your custom design then the sequence would be:

1) Understand the refclk pin used for the driving the channels from the Schematics. I believe these are F-tile FHT channel XCVR pins.

2) Trace the refclk pin to its source. It must be connected to one of the OUT pins of the clock source. Example: Si5394 (U118) OUT0.

3) Click on the "Clock" button under Utilities box on the BTS home page.

4) Locate the source IC (Si5394) from the multiple tabs: 4.3. Control On-Board Clock through Clock Controller GUI

5) Change to the required frequency for 32G configured in the F-tile system PLL IP.

6) Make sure that the input data rate at the XCVR pin is as per the configuration in the F-tile DPHY IP.

Hope this helps.

Regards