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ming001
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6 months ago

How to set clock controller in BTS (board_test_system) for 32G (NRZ) MXP BTS example

Dear support: We expect the Agilex 7 FPGA I-Series F-Tile. All four channels can run at 32G NRZ and 58G PMA4. Currently, we use the factory default setting, and MXPM can run at 25.78118G without er...
Programmable Logic Device
ming001's avatar
ming001
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6 months ago

Hi Ash_R:

I provide more information as follows

1. The current BTS (board test system) has been configured as MXPM_FGT x4

(25.78118Gbps) , and the loopback function works well.


2. if we change the clock rate using the clock controller (ex. OUT2

156.25MHz-->148.5MHz (or 184.32MHz) ), the system hangs.

How to change the clock for MXPM_FGT x4 32Gbps ?

Thanks.

Regards,

Ming

  • ming001's avatar
    ming001
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    5 months ago

    Hi Ash_R:

    We have updated the sequence to setup the clock (out2 set 184.32MHz) by configuring the "clock controller" first, setting OUT2 to 184.32MHz. (see attached file)

    Next, we upload the "*.sof" (bts_mxpmn.sof) file to configure the FPGA for MXPM application.

    The FPGA is currently operating at a 30.41274Gbps data rate right now, however we are unsure how to configure

    the clock and achieve a 32Gbps data rate. it is very important for our application.

    Could you please advise us on how to resolve this issue?

    Thanks.

    Regards,

    Ming

    • ming001's avatar
      ming001
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      5 months ago

      Hi Ash_R:

      We still cannot figure out the solution to achieve a 32Gbps data rate.

      Could you kindly take a look at this issue?

      Really appreciate.

      Regards,

      Ming