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Honored Contributorhow to avoid this warning?
Recently,i am working with EPM570T10I,program with Verilog hdl.
When i compiler the code,but there is a warning in Quartus II: Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew. Info: Detected ripple clock "flg_oc_1" as buffer But,the signal "flg_oc_1" is not a clock in my design ,it is just a pulse signal。 How should i do to avoid the warning? THX!!!11 Replies
Altera_Forum--- Quote Start --- If you really wwant to get rid of the warning you could use the output of the FF ( used as clock) as an enable signal of the other FF. --- Quote End --- For a more thorough discussion of using clock enables instead of ripple or gated clocks, see http://www.alteraforum.com/forum/showthread.php?t=2388.- Altera_Forum--- Quote Start --- yes, you can ignore the warning. If you really wwant to get rid of the warning you could use the output of the FF ( used as clock) as an enable signal of the other FF. --- Quote End --- thank you very much，that‘s a great help for me。
- Altera_Forum--- Quote Start --- yeah，you are right,may i ignore the warning？The waveform of the simulation is that what i need. --- Quote End --- yes, you can ignore the warning. If you really wwant to get rid of the warning you could use the output of the FF ( used as clock) as an enable signal of the other FF.
- Altera_Forum--- Quote Start --- After looking into the RTL view of the Quartus project I found, that the output of the register is driving the clock input of another FF. Quartus has to treat this signal as a clock. The warning is correct. --- Quote End --- yeah，you are right,may i ignore the warning？The waveform of the simulation is that what i need.
- Altera_Forum--- Quote Start --- In your code you have tyhe following stuctures assign flg_oc_2 = flg_oc_1; always @ (posedge out_feed or posedge flg_oc_2) begin if (out_feed) begin flg_block_drive_1 <= 1'b0; end else if (flg_oc_2) begin flg_block_drive_1 <= 1'b1; end end You may be assuming that flg_oc_2 is just a strobe but in fact the coding style infers a clock! The above code will infer a FlipFlop for flg_block_drive_1 with flg_oc_2 as a clock input. So the warning is correct. Hope this helps --- Quote End --- After looking into the RTL view of the Quartus project I found, that the output of the register is driving the clock input of another FF. Quartus has to treat this signal as a clock. The warning is correct.
- Altera_Forum
In your code you have tyhe following stuctures
assign flg_oc_2 = flg_oc_1; always @ (posedge out_feed or posedge flg_oc_2) begin if (out_feed) begin flg_block_drive_1 <= 1'b0; end else if (flg_oc_2) begin flg_block_drive_1 <= 1'b1; end end You may be assuming that flg_oc_2 is just a strobe but in fact the coding style infers a clock! The above code will infer a FlipFlop for flg_block_drive_1 with flg_oc_2 as a clock input. So the warning is correct. Hope this helps - Altera_Forum--- Quote Start --- hi,i do not define any setting excepting for the setting "not a clock". The code: module over_current_check ( clk_1m, over_current_signal, rst_n, flg_block_drv, flg_over_current ); parameter CNT_FORTY = 6'b101_000, CNT_TWO_THOUSAND = 15'b100_111_000_100_000; input wire clk_1m; input wire over_current_signal; input wire rst_n; output wire flg_block_drv; //over current,disable drive output 20ms output wire flg_over_current; wire flg_oc_2; reg flg_oc_1; //if the over_current_signal keep low for 40us,flg_oc_1 keep high level 1us reg out_feed; reg flg_block_drive_1; //if flg_oc_1 is high,flg_block_drive_1 keep high for 20ms reg [5:0] cnt_40; reg [14:0] cnt_20000; always @ (posedge clk_1m) begin if (!rst_n) begin cnt_40 <= 6'b000000; flg_oc_1 <= 1'b0; end else begin if (!over_current_signal) begin if (cnt_40 == CNT_FORTY) begin cnt_40 <= 6'b000000; flg_oc_1 <= 1'b1; end else begin cnt_40 <= cnt_40 + 6'b000001; flg_oc_1 <= 1'b0; end end else begin cnt_40 <= 6'b000000; flg_oc_1 <= 1'b0; end end end assign flg_oc_2 = flg_oc_1; always @ (posedge out_feed or posedge flg_oc_2) begin if (out_feed) begin flg_block_drive_1 <= 1'b0; end else if (flg_oc_2) begin flg_block_drive_1 <= 1'b1; end end always @ (posedge clk_1m) begin if (!flg_block_drive_1) begin cnt_20000 <= 15'b000_000_000_000_000; out_feed <= 1'b0; end else if (flg_block_drive_1) begin if (cnt_20000 == CNT_TWO_THOUSAND) begin out_feed <= 1'b1; cnt_20000 <= 15'b000000000000000; end else begin cnt_20000 <= cnt_20000 + 15'b000000000000001; end end end assign flg_block_drv = flg_block_drive_1; assign flg_over_current = flg_oc_1; endmodule --- Quote End --- Hi, you are right , the "not a clock" is only valid for I/O's. It is not valid for internal nodes, therefore the additional warning.
- Altera_Forum
hi,i do not define any setting excepting for the setting "not a clock".
The code: module over_current_check ( clk_1m, over_current_signal, rst_n, flg_block_drv, flg_over_current ); parameter CNT_FORTY = 6'b101_000, CNT_TWO_THOUSAND = 15'b100_111_000_100_000; input wire clk_1m; input wire over_current_signal; input wire rst_n; output wire flg_block_drv; //over current,disable drive output 20ms output wire flg_over_current; wire flg_oc_2; reg flg_oc_1; //if the over_current_signal keep low for 40us,flg_oc_1 keep high level 1us reg out_feed; reg flg_block_drive_1; //if flg_oc_1 is high,flg_block_drive_1 keep high for 20ms reg [5:0] cnt_40; reg [14:0] cnt_20000; always @ (posedge clk_1m) begin if (!rst_n) begin cnt_40 <= 6'b000000; flg_oc_1 <= 1'b0; end else begin if (!over_current_signal) begin if (cnt_40 == CNT_FORTY) begin cnt_40 <= 6'b000000; flg_oc_1 <= 1'b1; end else begin cnt_40 <= cnt_40 + 6'b000001; flg_oc_1 <= 1'b0; end end else begin cnt_40 <= 6'b000000; flg_oc_1 <= 1'b0; end end end assign flg_oc_2 = flg_oc_1; always @ (posedge out_feed or posedge flg_oc_2) begin if (out_feed) begin flg_block_drive_1 <= 1'b0; end else if (flg_oc_2) begin flg_block_drive_1 <= 1'b1; end end always @ (posedge clk_1m) begin if (!flg_block_drive_1) begin cnt_20000 <= 15'b000_000_000_000_000; out_feed <= 1'b0; end else if (flg_block_drive_1) begin if (cnt_20000 == CNT_TWO_THOUSAND) begin out_feed <= 1'b1; cnt_20000 <= 15'b000000000000000; end else begin cnt_20000 <= cnt_20000 + 15'b000000000000001; end end end assign flg_block_drv = flg_block_drive_1; assign flg_over_current = flg_oc_1; endmodule - Altera_Forum--- Quote Start --- THX for your help first.The method you mentioned above i have tried，but the warning is still，and another warning happens： Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details。 No timing path applicable to specified destination。 By the way，the signal “flg_oc_1” is a internal variable，not a IO。 --- Quote End --- hi, it looks like that you have a clock setting defined for this signal (?), but you defined now that it is not clock. The constraint is no longer applicable.
- Altera_Forum--- Quote Start --- Hi, if you really would to get rid of the warning you can use the assignment editor: Assignments -> Assignments Editor -> ( fill in node name in the "to" column) -> choose assignment "not a clock". Don't forget to set the Value to "on". --- Quote End --- THX for your help first.The method you mentioned above i have tried，but the warning is still，and another warning happens： Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details。 No timing path applicable to specified destination。 By the way，the signal “flg_oc_1” is a internal variable，not a IO。
