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Altera_Forum
Honored Contributor
18 years agohow to avoid this warning?
Recently,i am working with EPM570T10I,program with Verilog hdl. When i compiler the code,but there is a warning in Quartus II: Warning: Found 1 node(s) in clock paths which may be acting as...
Altera_Forum
Honored Contributor
18 years ago --- Quote Start --- Hi, if you really would to get rid of the warning you can use the assignment editor: Assignments -> Assignments Editor -> ( fill in node name in the "to" column) -> choose assignment "not a clock". Don't forget to set the Value to "on". --- Quote End --- THX for your help first.The method you mentioned above i have tried,but the warning is still,and another warning happens: Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details。 No timing path applicable to specified destination。 By the way,the signal “flg_oc_1” is a internal variable,not a IO。