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Honored Contributor
Honored Contributorhow to avoid this warning?
Recently,i am working with EPM570T10I,program with Verilog hdl. When i compiler the code,but there is a warning in Quartus II: Warning: Found 1 node(s) in clock paths which may be acting as...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- After looking into the RTL view of the Quartus project I found, that the output of the register is driving the clock input of another FF. Quartus has to treat this signal as a clock. The warning is correct. --- Quote End --- yeah，you are right,may i ignore the warning？The waveform of the simulation is that what i need.
