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Honored Contributor
Honored Contributorhow to avoid this warning?
Recently,i am working with EPM570T10I,program with Verilog hdl. When i compiler the code,but there is a warning in Quartus II: Warning: Found 1 node(s) in clock paths which may be acting as...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- THX for your help first.The method you mentioned above i have tried，but the warning is still，and another warning happens： Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details。 No timing path applicable to specified destination。 By the way，the signal “flg_oc_1” is a internal variable，not a IO。 --- Quote End --- hi, it looks like that you have a clock setting defined for this signal (?), but you defined now that it is not clock. The constraint is no longer applicable.
