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Altera_Forum's avatar
Altera_Forum
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18 years ago

how to avoid this warning?

Recently,i am working with EPM570T10I,program with Verilog hdl. When i compiler the code,but there is a warning in Quartus II: Warning: Found 1 node(s) in clock paths which may be acting as...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

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yes, you can ignore the warning. If you really wwant to get rid of the warning you could use the output of the FF ( used as clock) as an enable signal of the other FF.

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thank you very much，that‘s a great help for me。