--- Quote Start ---
hi,i do not define any setting excepting for the setting "not a clock".
The code:
module over_current_check (
clk_1m,
over_current_signal,
rst_n,
flg_block_drv,
flg_over_current
);
parameter CNT_FORTY = 6'b101_000,
CNT_TWO_THOUSAND = 15'b100_111_000_100_000;
input wire clk_1m;
input wire over_current_signal;
input wire rst_n;
output wire flg_block_drv; //over current,disable drive output 20ms
output wire flg_over_current;
wire flg_oc_2;
reg flg_oc_1; //if the over_current_signal keep low for 40us,flg_oc_1 keep high level 1us
reg out_feed;
reg flg_block_drive_1; //if flg_oc_1 is high,flg_block_drive_1 keep high for 20ms
reg [5:0] cnt_40;
reg [14:0] cnt_20000;
always @ (posedge clk_1m)
begin
if (!rst_n)
begin
cnt_40 <= 6'b000000;
flg_oc_1 <= 1'b0;
end
else
begin
if (!over_current_signal)
begin
if (cnt_40 == CNT_FORTY)
begin
cnt_40 <= 6'b000000;
flg_oc_1 <= 1'b1;
end
else
begin
cnt_40 <= cnt_40 + 6'b000001;
flg_oc_1 <= 1'b0;
end
end
else
begin
cnt_40 <= 6'b000000;
flg_oc_1 <= 1'b0;
end
end
end
assign flg_oc_2 = flg_oc_1;
always @ (posedge out_feed or posedge flg_oc_2)
begin
if (out_feed)
begin
flg_block_drive_1 <= 1'b0;
end
else if (flg_oc_2)
begin
flg_block_drive_1 <= 1'b1;
end
end
always @ (posedge clk_1m)
begin
if (!flg_block_drive_1)
begin
cnt_20000 <= 15'b000_000_000_000_000;
out_feed <= 1'b0;
end
else if (flg_block_drive_1)
begin
if (cnt_20000 == CNT_TWO_THOUSAND)
begin
out_feed <= 1'b1;
cnt_20000 <= 15'b000000000000000;
end
else
begin
cnt_20000 <= cnt_20000 + 15'b000000000000001;
end
end
end
assign flg_block_drv = flg_block_drive_1;
assign flg_over_current = flg_oc_1;
endmodule
--- Quote End ---
Hi,
you are right , the "not a clock" is only valid for I/O's. It is not valid for internal nodes, therefore the additional warning.
Honored Contributor
