Generate patterns through CPLD(MAXII)?

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Ok, I will switch my platform from CPLD to FPGA. And I prefer to have USB as the interface input string from laptop. Ecexpt DE0 board, what Kinds of hardware or IPs I should prepare to implement the test pattern generator?

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Provide a better description on what the patterns are supposed to be and we can provide a better answer. For example, do you have hundreds of individual bits/wires that you need to generate patterns on, are the patterns all the same, what frequency do you need to generate the patterns at?

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My target: To have simple access to MCUs, in which, most of them are ARM based.

1. Enter some low power modes of MCUs

2. Access to their embflash memory, however, simple access would be enough.

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The ARM MCUs already come with these features, why do you need an FPGA?

Cheers,

Dave

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Then you definitely need a FPGA.

Using buttons or generic I/Os was only an idea for a very simple solution.

Sure you can do it with a laptop!

For example you can send the pattern and control the generator with the RS232 serial port.

The jtag interface solution suggested by Dave is also good, but this can be used if you only need the pattern generator connected to your laptop. If you plan to deploy the design in a commercial board, you must provide a standard widely used interface:

in this case, besides RS232 you can implement virtually everything with fpga, from PCI to Ethernet, USB and so on.

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Thanks, Cris!

Ok, I will switch my platform from CPLD to FPGA. And I prefer to have USB as the interface input string from laptop. Ecexpt DE0 board, what Kinds of hardware or IPs I should prepare to implement the test pattern generator?

My target: To have simple access to MCUs, in which, most of them are ARM based.

1. Enter some low power modes of MCUs

2. Access to their embflash memory, however, simple access would be enough.

Best regards,

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Chris,

1. It might be hundreds of bits for a input string.

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Then you definitely need a FPGA.

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2. Is it must to use external controls (push buttons, PLC or MCU outputs)? Can I input the string simply from the master (laptop)?

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Using buttons or generic I/Os was only an idea for a very simple solution.

Sure you can do it with a laptop!

For example you can send the pattern and control the generator with the RS232 serial port.

The jtag interface solution suggested by Dave is also good, but this can be used if you only need the pattern generator connected to your laptop. If you plan to deploy the design in a commercial board, you must provide a standard widely used interface:

in this case, besides RS232 you can implement virtually everything with fpga, from PCI to Ethernet, USB and so on.

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I can have 8Mbits SDRAM from DE0 board, but I don't know if this is dual-port. Also, I need to purchase Avalon-MM IP. Right?

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I don't think you'll need to use the off-chip RAM unless your patterns are really long. If they are, then no problem, you can use the SDRAM controller provided by Altera, and a DMA controller within the FPGA to stream from the SDRAM controller to a FIFO target, and the other side of that FIFO can be your test pattern logic generator.

If you need random patterns then you can use a linear feedback shift register to do the job:

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf

Cheers,

Dave

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Here's what I'd do with a DE0-nano (DE0, DE1, DE2, ...);

1) Use the JTAG-to-Avalon-MM master interface to provide host-to-FPGA communications. (I'm finishing off a tutorial on how to do this, I'll post it soon).

2) Use a dual-ported RAM, with one side mapped as a Avalon-MM slave, and the other side connected to your test pattern logic; the test pattern logic would read a parallel word from RAM, and then write that to I/O pins, or shift it, or whatever you need it to do.

3) Have an Avalon-MM slave for some control registers, to enable your test pattern generator, and monitor when it is done (or your test fails).

4) Wire up your test pattern pins to the device under test, and wire response pins back to your DE0-nano.

5) Either capture the response in RAM, or use a Signal Tap II instance.

This is basically what I use for testing transceiver interfaces on the Stratix IV GX devices.

Cheers,

Dave

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Thanks for the suggestion, Dave.

This means that I have a lot of things to learn.

I can have 8Mbits SDRAM from DE0 board, but I don't know if this is dual-port. Also, I need to purchase Avalon-MM IP. Right?

Regards,

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You must specify what do you mean for medium size: tens of bits, hundreds, thousands?

The optimal solution is different in these cases.

I dare say that for a pattern less than 100bits long which needs to be changed occasionally you can simply use a CPLD and the shift register solution.

Usually the shift register blocks (I refer now to lpm_shiftreg) have a LOAD input which loads all data from a parallel port and/or a SHIFTIN input to load serially.

For each clock edge, stored data is sent serially out of a SHIFTOUT port, and this is the pattern you want to generate.

Parallel load is not convenient in your case; discard it and connect all other shiftreg input ports to external controls (push buttons, PLC or microcontroller outputs): you can do everything with these few signals.

PLease note that minimal extra logic inside CPLD may be required if you need the pattern to be generated under particular conditions.

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Chris,

1. It might be hundreds of bits for a input string.

2. Is it must to use external controls (push buttons, PLC or MCU outputs)? Can I input the string simply from the master (laptop)?

Thanks!

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My expectation would be medium size test pattern. It won't be fixed pattern but might subject to modification while test different chips. In most cases, these patterns are not complicated.

I'm checking shift register's block function, but I don't know how to generate patterns. Since normal DFF provides shift register function, how can I generate an input string?

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Here's what I'd do with a DE0-nano (DE0, DE1, DE2, ...);

1) Use the JTAG-to-Avalon-MM master interface to provide host-to-FPGA communications. (I'm finishing off a tutorial on how to do this, I'll post it soon).

2) Use a dual-ported RAM, with one side mapped as a Avalon-MM slave, and the other side connected to your test pattern logic; the test pattern logic would read a parallel word from RAM, and then write that to I/O pins, or shift it, or whatever you need it to do.

3) Have an Avalon-MM slave for some control registers, to enable your test pattern generator, and monitor when it is done (or your test fails).

4) Wire up your test pattern pins to the device under test, and wire response pins back to your DE0-nano.

5) Either capture the response in RAM, or use a Signal Tap II instance.

This is basically what I use for testing transceiver interfaces on the Stratix IV GX devices.

Cheers,

Dave

You must specify what do you mean for medium size: tens of bits, hundreds, thousands?

The optimal solution is different in these cases.

I dare say that for a pattern less than 100bits long which needs to be changed occasionally you can simply use a CPLD and the shift register solution.

Usually the shift register blocks (I refer now to lpm_shiftreg) have a LOAD input which loads all data from a parallel port and/or a SHIFTIN input to load serially.

For each clock edge, stored data is sent serially out of a SHIFTOUT port, and this is the pattern you want to generate.

Parallel load is not convenient in your case; discard it and connect all other shiftreg input ports to external controls (push buttons, PLC or microcontroller outputs): you can do everything with these few signals.

PLease note that minimal extra logic inside CPLD may be required if you need the pattern to be generated under particular conditions.

My expectation would be medium size test pattern. It won't be fixed pattern but might subject to modification while test different chips. In most cases, these patterns are not complicated.

I'm checking shift register's block function, but I don't know how to generate patterns. Since normal DFF provides shift register function, how can I generate an input string?

How long is the pattern you need to generate?

Is a fixed pattern or do you need to change it?

In the simplest cases a CPLD would be enough: I mean if you have a medium-short fixed pattern or a well defined set of short patterns.

The more complex is the pattern generator, the bigger the device you'll need.

I'd suggest a device like EP3C16F484 or similar range if you want a generator with a lot of features, possibly controlled through Ethernet or serial port.

If you instead need only a simple push-button-and-generate-pattern device, stick on a CPLD.