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My expectation would be medium size test pattern. It won't be fixed pattern but might subject to modification while test different chips. In most cases, these patterns are not complicated.
I'm checking shift register's block function, but I don't know how to generate patterns. Since normal DFF provides shift register function, how can I generate an input string?
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Here's what I'd do with a DE0-nano (DE0, DE1, DE2, ...);
1) Use the JTAG-to-Avalon-MM master interface to provide host-to-FPGA communications. (I'm finishing off a tutorial on how to do this, I'll post it soon).
2) Use a dual-ported RAM, with one side mapped as a Avalon-MM slave, and the other side connected to your test pattern logic; the test pattern logic would read a parallel word from RAM, and then write that to I/O pins, or shift it, or whatever you need it to do.
3) Have an Avalon-MM slave for some control registers, to enable your test pattern generator, and monitor when it is done (or your test fails).
4) Wire up your test pattern pins to the device under test, and wire response pins back to your DE0-nano.
5) Either capture the response in RAM, or use a Signal Tap II instance.
This is basically what I use for testing transceiver interfaces on the Stratix IV GX devices.
Cheers,
Dave
Honored Contributor
