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I can have 8Mbits SDRAM from DE0 board, but I don't know if this is dual-port. Also, I need to purchase Avalon-MM IP. Right?
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I don't think you'll need to use the off-chip RAM unless your patterns are really long. If they are, then no problem, you can use the SDRAM controller provided by Altera, and a DMA controller within the FPGA to stream from the SDRAM controller to a FIFO target, and the other side of that FIFO can be your test pattern logic generator.
If you need random patterns then you can use a linear feedback shift register to do the job:
http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf Cheers,
Dave
Honored Contributor
