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Altera_Forum
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14 years ago

Generate patterns through CPLD(MAXII)?

I'm new to FPGA/CPLD. Could any one help me? I'm wondering if I can use CPLD/FPGA to generate some patterns to output pins? This is for some simple test purpose. For example, under 50MHz clo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

My expectation would be medium size test pattern. It won't be fixed pattern but might subject to modification while test different chips. In most cases, these patterns are not complicated.

I'm checking shift register's block function, but I don't know how to generate patterns. Since normal DFF provides shift register function, how can I generate an input string?