Frequency divider with clk en.

Could you post a code fragment of your counter. It would really help with solving your problem.

Have you considered using a PLL for your frequency divider?

Rgds

It sounds like you're using the output of a register in your divider to act as a clock, hence the warning.

The clock enable method means that, for example, to generate your (approx.) 560kHz clock, you should actually generate a clock enable signal which goes high for one clock cycle in every 89. You then use this signal along with the original 50Mhz clock to drive whatever logic needs the slower clock. You then just have to make sure that this logic only responds to clock edges when clock enable is high. In Verilog it would be something like this:

always @ (posedge clk)

begin

if(clk_en)

// Do whatever

Now, I'm considering a PLL like freq divider, Do you have information about it ? (I'm using DE1 board).

Thanks vernmid.

sharkybaba,

Yes, I'm using the output of a register like a clk.

How can I generate a signal every 89 ?

Where the 50Mhz clk is connected ?

Thanks a lot.

Chema,

My apologies, I misread your post!

You will not be able to use a PLL to divide 50MHz to 560KHz.

Stick with the counter as suggested (CLocked from your 50MHz). Count 0 to 43 then make an output low, count 0 to 44 then make the output high etc etc. Gives a slightly uneven Mark/Space ratio but this probable isn't an issue for you.

Once again, sorry for the duff steer

vernmid, Here is the code:

process(clk)

begin

if (clk'event and clk='1') then

counter<=counter + 1;

if counter=44 then

freq_div<=not(freq_div);

counter<=1;

end if;

end if;

end process;

I was reading that this is not the best way for a freq divider;

All suggestions are about PLL and clk enable method, maybe clk enable is the easiest way.....but I don't have information about it, thanks.

Looks OK.

The other suggestion (What sharkybaba suggested) is to generate a clock enable rather than a clock.

For example use your counter to generate a pulse that is high for 1 clock and low for 88. i.e. a pulse generator rather a clock generator.

In the logic you need to be clocked at the slow clock, use something like

process(clk)

begin

if (clk'event and clk='1') then

if (clk_en = '1') then

-- what ever you want

-- clk en is the output pulse from your divider

end if;

end if;

end process;

In effect everything is still clocked from the 50MHz clock but you have generated a clock enable

That's the said clock enable method as a complete process block

process (clk)
begin
if rising_edge(clk) then --the convenient short cut
-- 50 MHz Fast action
  if counter=88 then
    counter<=1;
    clk_en_568k = '1';
  else
    counter<=counter + 1;
    clk_en_568k = '0'; 
  end if;
  if clk_en_568k = '1' then
  -- 566k Slow action
  end if;
end if;
end;

I guess, that you had something like

if (freq_div'event and freq_div='1') then

before. That's what the synthesis tool was actually complaining about.

Cause the freq_div, the ripple clock is delayed to clk, you have problems to process signals from the 50 MHz domain in the 568 kHz domain. They are changing state exactly at the clock edge, violating setup and hold times.

FvM,

I was working with your code but I get the same warning.

What a I want to do is a subsystem with a 560kHz clock output and a 18 bits output changing the value with the 560kHz freq too. This subsystem is connected to a cordic block, the 18 bits output is the angle for cordic and the 560kHz output is the work freq of cordic block.

--- Quote Start ---

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_unsigned.all;

entity CE_div is

Port (

clk: in std_logic;

angle_out: buffer std_logic_vector(17 downto 0):="000000000000000000";

clk_en_568k: buffer std_logic

);

end CE_div;

architecture behav of CE_div is

signal counter: integer range 1 to 88;

begin

process (clk)

begin

if rising_edge(clk) then --the convenient short cut

-- 50 MHz Fast action

if counter=2 then

counter<=1;

clk_en_568k <= '1';

else

counter<=counter + 1;

clk_en_568k <= '0';

end if;

if clk_en_568k = '1' then

-- 566k Slow action

angle_out <= angle_out + "000000010000000101";

if (angle_out="011001001000011111" or angle_out>"011001001000011111" )then

angle_out<="000000000000000000";

end if;

end if;

end if;

end process;

end;

--- Quote End ---

The warnings are:

- Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew

- Warning: Circuit may not operate. Detected 5 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.

Thanks for your answers...