Frequency divider with clk en.

Looks OK.

The other suggestion (What sharkybaba suggested) is to generate a clock enable rather than a clock.

For example use your counter to generate a pulse that is high for 1 clock and low for 88. i.e. a pulse generator rather a clock generator.

In the logic you need to be clocked at the slow clock, use something like

process(clk)

begin

if (clk'event and clk='1') then

if (clk_en = '1') then

-- what ever you want

-- clk en is the output pulse from your divider

end if;

end if;

end process;

In effect everything is still clocked from the 50MHz clock but you have generated a clock enable