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Honored Contributor
Honored ContributorFrequency divider with clk en.
I want to make a frequency divider (50 Mhz to any value, 560khz ), I am working with a counter like a freq. divider but there is a warning in Quartus II: Warning: Found 1 node(s) in clock pat...
Altera_ForumHonored Contributor
Honored ContributorChema,
My apologies, I misread your post! You will not be able to use a PLL to divide 50MHz to 560KHz. Stick with the counter as suggested (CLocked from your 50MHz). Count 0 to 43 then make an output low, count 0 to 44 then make the output high etc etc. Gives a slightly uneven Mark/Space ratio but this probable isn't an issue for you. Once again, sorry for the duff steer
