Frequency divider with clk en.

FvM,

I was working with your code but I get the same warning.

What a I want to do is a subsystem with a 560kHz clock output and a 18 bits output changing the value with the 560kHz freq too. This subsystem is connected to a cordic block, the 18 bits output is the angle for cordic and the 560kHz output is the work freq of cordic block.

--- Quote Start ---

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_unsigned.all;

entity CE_div is

Port (

clk: in std_logic;

angle_out: buffer std_logic_vector(17 downto 0):="000000000000000000";

clk_en_568k: buffer std_logic

);

end CE_div;

architecture behav of CE_div is

signal counter: integer range 1 to 88;

begin

process (clk)

begin

if rising_edge(clk) then --the convenient short cut

-- 50 MHz Fast action

if counter=2 then

counter<=1;

clk_en_568k <= '1';

else

counter<=counter + 1;

clk_en_568k <= '0';

end if;

if clk_en_568k = '1' then

-- 566k Slow action

angle_out <= angle_out + "000000010000000101";

if (angle_out="011001001000011111" or angle_out>"011001001000011111" )then

angle_out<="000000000000000000";

end if;

end if;

end if;

end process;

end;

--- Quote End ---

The warnings are:

- Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew

- Warning: Circuit may not operate. Detected 5 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.

Thanks for your answers...