Frequency divider with clk en.

That's the said clock enable method as a complete process block

process (clk)
begin
if rising_edge(clk) then --the convenient short cut
-- 50 MHz Fast action
  if counter=88 then
    counter<=1;
    clk_en_568k = '1';
  else
    counter<=counter + 1;
    clk_en_568k = '0'; 
  end if;
  if clk_en_568k = '1' then
  -- 566k Slow action
  end if;
end if;
end;

I guess, that you had something like

if (freq_div'event and freq_div='1') then

before. That's what the synthesis tool was actually complaining about.

Cause the freq_div, the ripple clock is delayed to clk, you have problems to process signals from the 50 MHz domain in the 568 kHz domain. They are changing state exactly at the clock edge, violating setup and hold times.