Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Frequency divider with clk en.

I want to make a frequency divider (50 Mhz to any value, 560khz ), I am working with a counter like a freq. divider but there is a warning in Quartus II:

Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew

I read that using a CLK EN is the best way to make a freq. divider, but a I don't know nothing about it, DO YOU HAVE INFORMATION OR EXAMPLES ABOUT? HELP ME PLEASE

13 Replies

Show More
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Ok, if I compile only this code there is no problem, the problem is when I connect this freq divider with the cordic block (I am working with schematic diagram). Each block, cordic and freq divider, works fine individually.

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Are you trying to clock the cordic block using the clk_en_568k signal by any chance? What you need to do is clock the cordic block from your 50MHz clock, and supply clk_en_568k to the cordic block as a clock enable signal. If the cordic block doesn't have a clock enable you'll have to modify it to add one.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Thanks !!!!!!!!!

    It was the solution sharkybba, cordic with clock enable ......

    Thanks to all for your help.....