Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Frequency divider with clk en.

I want to make a frequency divider (50 Mhz to any value, 560khz ), I am working with a counter like a freq. divider but there is a warning in Quartus II: Warning: Found 1 node(s) in clock pat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

vernmid, Here is the code:

process(clk)

begin

if (clk'event and clk='1') then

counter<=counter + 1;

if counter=44 then

freq_div<=not(freq_div);

counter<=1;

end if;

end if;

end process;

I was reading that this is not the best way for a freq divider;

All suggestions are about PLL and clk enable method, maybe clk enable is the easiest way.....but I don't have information about it, thanks.