Frequency divider with clk en.

It sounds like you're using the output of a register in your divider to act as a clock, hence the warning.

The clock enable method means that, for example, to generate your (approx.) 560kHz clock, you should actually generate a clock enable signal which goes high for one clock cycle in every 89. You then use this signal along with the original 50Mhz clock to drive whatever logic needs the slower clock. You then just have to make sure that this logic only responds to clock edges when clock enable is high. In Verilog it would be something like this:

always @ (posedge clk)

begin

if(clk_en)

// Do whatever