Altera_Forum
Honored Contributor
15 years agoFPGA specific timing requirement
I need to output a pulse signal from the FPGA that is very time sensitive. I would like to have control of the period by a resolution of 2 ns. This would require a 500 MHz output clock. Briefly looking at the cyclone III, it seems that this is not possible; however, it says it can reach 400 MHz, which might be good enough.
I'm wondering if there is a way to reach my goal of a 2 ns resolution using a cyclone III and if not is there another board that can achieve this? Also, if need be can I clock the cyclone III at 400 MHz to be used as the timer for the period? I have seen a lot of posts regarding that even though the specs say it can be clocked at certain speeds, the circuit might not work correctly at those speeds. Any help will be greatly appreciated.