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Altera_Forum's avatar
Altera_Forum
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15 years ago

FPGA specific timing requirement

I need to output a pulse signal from the FPGA that is very time sensitive. I would like to have control of the period by a resolution of 2 ns. This would require a 500 MHz output clock. Briefly looki...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi,

Cyclone III supports DDR (Double Data Rate) outputs, so you can control a pulse's width in 2ns increments using a 250 MHz clock.

The maximum frequency that the FPGA will actually work correctly will depend on many things: design, I/O characteristics, etc.

The only way to know for sure is to implement a design and validate it using STA (Static Timming Analysis) and gate level simulation.

Important question: what kind of signals are you using? LVCMOS? LVDS?