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Altera_Forum
Honored Contributor
Honored ContributorFPGA specific timing requirement
I need to output a pulse signal from the FPGA that is very time sensitive. I would like to have control of the period by a resolution of 2 ns. This would require a 500 MHz output clock. Briefly looki...
Altera_ForumHonored Contributor
Honored ContributorEssentialy I would just be using the rising and falling edges of the clock instead of just the rising?
