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Altera_Forum's avatar
Altera_Forum
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16 years ago

FPGA specific timing requirement

I need to output a pulse signal from the FPGA that is very time sensitive. I would like to have control of the period by a resolution of 2 ns. This would require a 500 MHz output clock. Briefly looki...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Essentially, if I had a worse case scenario and my input wave was 400KHz, which is 2.5 us period. If I wanted to produce an output of a pulse from two different signals at 2.499 us or basically turn one pulse on for x of time then off and then turn the other on for x and then off and have this period be 2.449 us. Is that doable? Also, could I do even better, lets say 0.5 ns?

My thoughts were to use a counter. I read some posts where people mentioned using 4 different phase changed clocks at 250MHzto achieve a 1GHz rate. Is that something that will work for me?