FPGA specific timing requirement

Yes, using both edges of the clock.

By better, I meant a bit better than 2 ns but way above 1 ns.

In the end, your resolutions is going to be limited not just by FPGAs internals but also by the signal's rise/fall time, noise, etc.

If the on time or the off time is very short (say, 2 ns), you might run into minimum pulse width issues, if you're using, say, 3.3 LVCMOS signals.

Board design will be important.

I'm not seeing how to combine 4 clocks with different phases to produce a better resolution.

It may be possible, but I don't see how.