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Altera_Forum's avatar
Altera_Forum
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15 years ago

FPGA specific timing requirement

I need to output a pulse signal from the FPGA that is very time sensitive. I would like to have control of the period by a resolution of 2 ns. This would require a 500 MHz output clock. Briefly looki...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

All digital signals are just "square" waves that are high and low... :)

You must understand that you are getting close to the limits of what FPGAs can do and weather what you need can be done or not, depends on the fine details.

Signal type may matter, both inputs and outputs. There are physical and hardware limitations and those limitations are different for different types of signal.

ie, CMOS signals are larger and cause more noise than LVDS. Thus, LVDS signals can be used at much higher frequencies than CMOS.

Anyway, I'm still trying to grap what you need to do.

Do you need to produce a square wave (that is, a clock like signal) and control the period with a 2ns resolution?

Or do you need to produce pulses of "1" where the pulse length is controlled to a 2ns resolution?