Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

FPGA specific timing requirement

I need to output a pulse signal from the FPGA that is very time sensitive. I would like to have control of the period by a resolution of 2 ns. This would require a 500 MHz output clock. Briefly looki...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

If I understood your needs correctly, it can be done.

Basically, what you need to do is use a 250 MHz (4ns) clock and DDR outputs. With DDR outputs, you can set a different value for each half of the clock cycle, thus you get your 2ns resolution.

You can even go higher than that.