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Honored ContributorFPGA configuration time and PCIe secification
Has anyone used the PCIe interface of a Cyclone device while configuring it using the AS (active serial) scheme?
I'm using a Cyclone IV device (EP4CGX30F484) and planning to use its PCIe interface. I've read from the PCIe specification that the minimum time between the PC's power rails being stable and the PCIe PERST# signal being deactivated is T_PVPERL = 100 ms (acitvating and deactivating PERST# causes a reset of the PCIe interface and causes PCIe lanes to initialise). You get another 100 ms from receiving the PERST# signal before the sequence starts, so that's a total of 200 ms. The PCIe specification only states a minimum time between power being stable and sending the PERST# signal, so you could get a few seconds before you have to be ready, but I don't know if I can rely on this. Using the active serial configuration scheme would take me 1.225 s, so it seems I have to use a different scheme, such as FPP. Altera recommend this in their application note AN529: “For Cyclone IV GX devices to meet the PCIe 100 ms wake-up time requirement, you must use PS configuration mode for the EP4CGX15, EP4CGX22, and EP4CGX30 (except for F484 package) devices and FPP configuration mode for the EP4CGX30 (only for F484 package), EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 devices.” FPP is a pain because you need another chip to manage the configuration process and this chip (MAX II or a microprocessor) needs its own software. So my question is: has anyone got the PCIe interface to work reliably while their configuration takes over 200 ms? I'd also like to hear if you haven't! Thanks.54 Replies
Altera_Forum--- Quote Start --- What is "reset supervisor" delay inside the FPGA? --- Quote End --- Its the logic that implements POR. If you were to create a design with a RST# signal going into the FPGA, then you would typically use a reset supervisor IC to "debounce" the reset signal, eg., a push button. --- Quote Start --- I don't see any straight-forward statment in Handbook, that tells to add tRAMP + tPOR, that is 3ms + 9ms. --- Quote End --- Its a conservative calculation, i.e., if you select MSEL for "Fast" POR, then your power supplies have to meet the tRAMP time, and following that tPOR will occur. Arguably tRAMP is tPOR(min), so you could just use tPOR(max) = 9ms. However, if you're within 3ms of the 100ms requirement, you're too close, and your system would likely fail in many systems, since even the 100ms value is not a guarantee. Read the references in the PDF link I gave above. Cheers, Dave- Altera_Forum--- Quote Start --- Handbook says ( p.11-4 ): "The MSEL pin settings determine the POR time (tPOR) of the device.", but not tRAMP. --- Quote End --- If you select Fast POR, then your hardware design must meet tRAMP.
- Altera_Forum--- Quote Start --- Arguably tRAMP is tPOR(min), so you could just use tPOR(max) = 9ms. --- Quote End --- This is what I mean. --- Quote Start --- However, if you're within 3ms of the 100ms requirement, you're too close, and your system would likely fail in many systems, since even the 100ms value is not a guarantee. Read the references in the PDF link I gave above. --- Quote End --- What is the statistically proven safe border ( close to 100ms ) for a safe custom board enumeration in any PC?I UPD: In what references can I read about it?
- Altera_Forum--- Quote Start --- A MAX II CPLD plus a QSPI flash can easily operate at 12MHz, this means with FPP mode, there is no problem meeting the power-on requirement. MAX II CPLD EPM240M100C5N $6 --- Quote End --- I was considering that possibility. MAX II CPLD with PFL inside / QSPI flash / PS mode for EP4CGX22 / Configuration mode only won't fit into EPM240M100C5N. EPM540M100C5N @ 13.5 USD has to be used ... A more comfortable Configuration + Programming mode won't fit even into EPM540M100C5N. EPM2210 @ ~30 USD has to be used ... Are You sure, that PFL input Clock = 12MHz clock is enough for MAX II to configure EP4CGX22 from a single Quad SPI ( N25Q128A13ESE40G ) in PS within below 50 ms ( as a conservative approach )?
- Altera_Forum--- Quote Start --- MAX II CPLD with PFL inside / QSPI flash / PS mode for EP4CGX22 / Configuration mode only won't fit into EPM240M100C5N. --- Quote End --- I don't use the PFL component, its trivial to write a controller to read from QSPI flash and generate the FPP configuration cycles. Here's some information for previous controllers and tests I've done http://www.ovro.caltech.edu/~dwh/correlator/pdf/timequest_quad_spi_flash.pdf http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf I've written a configuration controller to read from QSPI flash and configure a Cyclone IV E in FPP mode. It uses 184 LCs. Cheers, Dave
- Altera_Forum--- Quote Start --- Are You sure, that PFL input Clock = 12MHz clock is enough for MAX II to configure EP4CGX22 from a single Quad SPI ( N25Q128A13ESE40G ) in PS within below 50 ms ( as a conservative approach )? --- Quote End --- The 12MHz was the minimum clock frequency. I'd run the design at 50MHz or 100MHz, whatever worked for your design, eg., use a clock frequency that you already have on the PCB. Cheers, Dave
- Altera_Forum--- Quote Start --- What is the statistically proven safe border ( close to 100ms ) for a safe custom board enumeration in any PCI? --- Quote End --- There is none :( PCI and PCIe are used in desktops, industrial backplanes (cPCI and CPCI-S.0), etc. The power supply designs for all of these systems are different. --- Quote Start --- In what references can I read about it? --- Quote End --- Read the references linked to on p4 of this document: http://www.ovro.caltech.edu/~dwh/wbsddc/ts4_power.pdf Some of those documents require buying the specifications, but if you're going to design boards, you need the specifications. Cheers, Dave
- Altera_Forum--- Quote Start --- I've written a configuration controller to read from QSPI flash and configure a Cyclone IV E in FPP mode. It uses 184 LCs. Cheers, Dave --- Quote End --- Do You share or sell it? UPD. Your custom controller is useless for my EP4CGX22. I need PS.
- Altera_Forum
Dave, Thank You for Your help!
To finish for today - maybe You have the formula to calculate configuration time for EP4CGX22 by MAX II from a single quad SPI flash ( N25Q128A13ESE40G ) in PS mode with PFL inside MAX II. PFL user guide ( p. 50 ) has the formula only for FPP. Or please tell what to modify in that formula so, that it can be used for PS instead of FPP. Thank You again! UPD. Formula is needed for PS mode with data compression. - Altera_Forum--- Quote Start --- Do You share or sell it? --- Quote End --- I'll share it. I need to look at the code and see whether I'd finished it, I got distracted and was working on something else. In your application, you want a MAX II plus QSPI Flash to configure a EP4CGX22, correct? --- Quote Start --- Your custom controller is useless for my EP4CGX22. I need PS. --- Quote End --- The only difference between PS and FPP is a shift-register. The controller handles both cases. Cheers, Dave
