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Altera_Forum
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13 years ago

FPGA configuration time and PCIe secification

Has anyone used the PCIe interface of a Cyclone device while configuring it using the AS (active serial) scheme? I'm using a Cyclone IV device (EP4CGX30F484) and planning to use its PCIe interf...
Altera_Forum's avatar
Altera_Forum
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12 years ago

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Are You sure, that PFL input Clock = 12MHz clock is enough for MAX II to configure EP4CGX22 from a single Quad SPI ( N25Q128A13ESE40G ) in PS within below 50 ms ( as a conservative approach )?

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The 12MHz was the minimum clock frequency. I'd run the design at 50MHz or 100MHz, whatever worked for your design, eg., use a clock frequency that you already have on the PCB.

Cheers,

Dave